Power Management Overview
PCIe implements comprehensive power management through two complementary mechanisms:
- Device Power Management (D-states): Software-controlled device power states
- Link Power Management (L-states): Hardware-controlled link power states
Why Power Management Matters
Modern systems spend most time idle. Effective power management reduces energy consumption, heat generation, and enables longer battery life in mobile devices.
Device Power States (D-States)
D0
Fully Operational
All features available
D1
Light Sleep
Optional, device-specific
D2
Deeper Sleep
Optional, more savings
D3hot
Software Off
Aux power, config preserved
D3cold
Power Removed
All power off
Link Power States (L-States)
| State | Description | Exit Latency | Control |
|---|---|---|---|
| L0 | Active - normal operation | N/A | N/A |
| L0s | Standby - quick recovery | < 1 µs | ASPM (hardware) |
| L0p | Partial bandwidth (PCIe 6.0+) | Varies | ASPM (hardware) |
| L1 | Low Power - deeper savings | < 32 µs | ASPM or PM software |
| L1.1 | L1 with PHY in low power | ~32 µs | L1 PM Substates |
| L1.2 | L1 with clocks stopped | ~100 µs | L1 PM Substates |
| L2 | Auxiliary power only | > 10 ms | PM software |
| L3 | Link off, power removed | > 100 ms | System |
Active State Power Management (ASPM)
ASPM allows hardware to autonomously transition the link to low-power states when idle.
ASPM Modes
- L0s Entry: Enabled per-direction independently
- L1 Entry: Both directions enter together
- L0s and L1: Both enabled
- Disabled: No automatic power management
L0s State
L0s is a low-latency standby state with very fast recovery (<1µs). Each direction can enter L0s independently.
- Transmitter stops sending data, sends EIOS
- Receiver detects EIOS and enters L0s
- Exit via FTS (Fast Training Sequence)
- Minimal power savings but very low latency
L1 State
L1 provides greater power savings than L0s but with higher exit latency.
- Both directions enter together
- Link clocks may be stopped
- Exit requires link retraining through Recovery
- Can be entered via ASPM or software PM
L1 PM Substates
L1 PM Substates provide even deeper power savings while in L1:
| Substate | Reference Clock | Common Mode | Power Savings |
|---|---|---|---|
| L1.0 | On | Maintained | Base L1 |
| L1.1 | On | Off | More |
| L1.2 | Off | Off | Maximum |
L0p State (PCIe 6.0+)
New in PCIe 6.0/7.0: L0p
L0p is a new partial-bandwidth state that reduces active lanes while maintaining some data transfer capability. This allows power savings without complete link quiescence.
- Reduces number of active lanes dynamically
- Faster transition than L1
- Maintains some bandwidth during low-traffic periods
PME Signaling
Power Management Events (PME) allow devices to wake the system:
- In-band PME: PM_PME message TLP
- WAKE# Signal: Sideband signal for D3cold wakeup
- Beacon: In-band wakeup from L2