Why Flit Mode?
PCIe 6.0 introduced Flit Mode as a fundamental architectural change to address the challenges of operating at 64 GT/s and beyond with PAM4 signaling.
The PAM4 Challenge
PAM4 signaling has inherently higher bit error rates than NRZ due to smaller voltage margins (3 eyes vs 1). The legacy per-TLP CRC approach would result in unacceptable packet loss rates at 64+ GT/s.
Solution: Fixed-size Flits with integrated FEC (Forward Error Correction) to correct errors before they cause packet loss.
Non-Flit Mode vs Flit Mode
| Aspect | Non-Flit Mode (Legacy) | Flit Mode (6.0+) |
|---|---|---|
| Packet Size | Variable (up to 4KB payload) | Fixed 256-byte Flits |
| Error Protection | LCRC per TLP | FEC + CRC per Flit |
| Error Handling | Detect & retransmit | Correct in-line, retransmit if needed |
| Encoding | 8b/10b or 128b/130b | 1b/1b PAM4 |
| Max Tags | 10-bit (1024) | 14-bit (16384) |
| DLLPs | Separate packets | Embedded in Flit DLP |
Flit Structure
A Flit (Flow Control Unit) is exactly 256 bytes, providing a fixed container for TLPs and control information.
Flit Types
Payload Flit (Type 00)
Contains TLP data. Multiple small TLPs can be packed into one Flit, or large TLPs span multiple Flits.
NOP Flit (Type 01)
Idle Flit sent when no TLP data available. Still carries DLP for flow control. Subtypes: NOP.Empty, NOP.Debug, NOP.Vendor.
ACK Flit (Type 10)
Explicit acknowledgment of received Flits. Contains sequence number being acknowledged.
NAK Flit (Type 11)
Request retransmission. Contains sequence number of missing/errored Flit.
TLP Packing in Flits
Multiple TLPs can be packed into a single Flit, and large TLPs span across Flit boundaries.
Forward Error Correction (FEC)
FEC is mandatory in Flit Mode and enables correction of bit errors without retransmission.
FEC Capabilities
- Error Correction: Corrects burst errors up to ~48 bits per Flit
- Latency Impact: Adds ~2-3 ns encoding/decoding latency
- Algorithm: Based on Reed-Solomon codes
- CRC Verification: After FEC decode, CRC verifies correction was successful
If FEC cannot correct errors (too many), the Flit fails CRC check and triggers NAK/retry.
Example: 10^-6 BER with 48-bit correction → effectively ~10^-12 Flit error rate
Flow Control Changes
Flit Mode changes flow control granularity from 16-byte FC units to 256-byte Flits.
Credit Changes
- Credit Unit: 1 credit = 1 Flit (256 bytes) instead of 4 DW (16 bytes)
- UpdateFC: Embedded in Flit DLP, not separate DLLPs
- Simpler Accounting: Fixed Flit size simplifies calculations
TLP Header Format Changes
Flit Mode optimizes TLP headers for efficiency.
8-Bit Type Field
Combined Fmt+Type into single 8-bit field. More encodings available for future expansion.
14-Bit Tags
Contiguous 14-bit Tag field supports 16,384 outstanding transactions.
OHC Field
5-bit Optimized Header Compression field indicates header compression mode.
No TH Bit
TPH (TLP Processing Hints) handled differently. TH bit removed from header.
Optimized Header Compression (OHC)
OHC reduces header overhead by allowing abbreviated headers when fields can be inferred.
14-Bit Tags
Flit Mode enables 14-bit Tags, dramatically increasing the number of outstanding transactions.
| Tag Size | Max Outstanding | Mode | Enable Bit |
|---|---|---|---|
| 5-bit | 32 | Both | Default |
| 8-bit | 256 | Both | Extended Tag Enable |
| 10-bit | 1,024 | Both | 10-Bit Tag Requester Enable |
| 14-bit | 16,384 | Flit Only | 14-Bit Tag Requester Enable |
ACK/NAK in Flit Mode
The ACK/NAK mechanism is adapted for Flit-level operation.
L0p Power State
Flit Mode introduces L0p, a new power state for partial bandwidth operation.
L0p (L0 Partial)
Allows reducing active lanes while maintaining L0 operation. Unlike L0s/L1, traffic continues on remaining lanes.
- Lane Reduction: x16 can reduce to x8, x4, x2, or x1
- Fast Transition: ~100ns to change width
- Continuous Operation: No entry/exit latency like L0s
- Power Savings: Linear with reduced lanes
Flit Mode Negotiation
Flit Mode is negotiated during link training.