Link Equalization Complete Guide

1. What is Link Equalization?

Link Equalization is the process of optimizing transmitter and receiver settings to compensate for channel impairments (loss, reflections, crosstalk) and achieve reliable data transmission at high speeds.

Why Equalization is Needed

Frequency-dependent loss: Higher frequencies attenuate more
Inter-Symbol Interference (ISI): Previous bits affect current bit
Reflections: Impedance mismatches cause reflections
Crosstalk: Adjacent lanes/traces couple energy

Equalization Required Speeds

Speed	Equalization	Phases
2.5 GT/s	Not required	-
5.0 GT/s	Not required	-
8.0 GT/s	Required	Phase 0-3
16.0 GT/s	Required	Phase 0-3
32.0 GT/s	Required	Phase 0-3
64.0 GT/s	Required (PAM4)	Extended
128.0 GT/s	Required (PAM4)	Extended

2. Equalization Components

Transmitter Equalization (Tx EQ)

3-tap Finite Impulse Response (FIR) filter:

                    ┌─────┐     ┌─────┐     ┌─────┐
    Input ─────────►│ Z⁻¹ │────►│ Z⁻¹ │────►│ Z⁻¹ │
                    └──┬──┘     └──┬──┘     └──┬──┘
                       │           │           │
                     ×C-1        ×C0         ×C+1
                   (pre)       (main)      (post)
                       │           │           │
                       └─────┬─────┴─────┬─────┘
                             │           │
                             ▼           ▼
                           ┌───────────────┐
                           │    Summer     │
                           └───────┬───────┘
                                   │
                                   ▼
                               Output

FIR Coefficients

Coefficient	Name	Function	Range
C-1	Pre-cursor	Cancels pre-cursor ISI	-0.1 to 0
C0	Main cursor	Primary signal level	0.5 to 1.0
C+1	Post-cursor	Cancels post-cursor ISI	-0.25 to 0

Receiver Equalization (Rx EQ)

CTLE: Continuous Time Linear Equalizer
- Analog front-end equalization
- High-frequency boost to compensate channel loss
- Programmable peaking frequency and gain
DFE: Decision Feedback Equalizer
- Cancels post-cursor ISI using past decisions
- Multiple taps (4-16 typical)
- Non-linear, doesn't boost noise

3. Equalization Phases

Phase 0 - Initial Preset

Downstream Port applies an initial Tx preset based on stored values or defaults.

Uses Transmitter Preset from configuration or default
Provides starting point for optimization
May bypass further phases if sufficient

Phase 1 - Upstream Evaluation

Upstream Port evaluates the Downstream Port's Tx signal and requests adjustments.

Upstream Rx evaluates received signal quality
Upstream requests Tx preset or coefficient changes
Uses Rx Preset Hint or coefficient request

Phase 2 - Downstream Evaluation

Downstream Port evaluates Upstream Port's Tx signal and requests adjustments.

Roles reversed from Phase 1
Downstream Rx evaluates Upstream Tx
Downstream requests adjustments

Phase 3 - Final Optimization

Optional fine-tuning phase for additional coefficient adjustments.

Both ports can request final adjustments
May iterate multiple times
Terminates when both satisfied or timeout

4. Tx Presets

Preset Definition

Presets are predefined combinations of FIR coefficients:

Preset	Pre-cursor	Main	Post-cursor	Description
P0	0.0	1.0	0.0	No equalization
P1	0.0	0.83	-0.17	Light de-emphasis
P2	0.0	0.75	-0.25	Moderate de-emphasis
P3	0.0	0.67	-0.33	Strong de-emphasis
P4	-0.08	0.75	-0.17	Pre + post cursor
...	...	...	...	Additional presets
P10	Varies	Varies	Varies	Full range

Preset Hints

Rx Preset Hints suggest which preset the link partner should use based on expected channel characteristics.

5. Equalization Procedure Flow

    Recovery.Equalization Entry
              │
              ▼
    ┌─────────────────────┐
    │      PHASE 0        │
    │  Apply Initial      │
    │  Tx Preset          │
    └──────────┬──────────┘
               │
               ▼
    ┌─────────────────────┐
    │      PHASE 1        │◄─────────────┐
    │  Upstream Port      │              │
    │  Evaluates DS Tx    │              │
    │  Requests Changes   │──────────────┘
    └──────────┬──────────┘   (iterate)
               │
               │ Upstream satisfied
               ▼
    ┌─────────────────────┐
    │      PHASE 2        │◄─────────────┐
    │  Downstream Port    │              │
    │  Evaluates US Tx    │              │
    │  Requests Changes   │──────────────┘
    └──────────┬──────────┘   (iterate)
               │
               │ Downstream satisfied
               ▼
    ┌─────────────────────┐
    │      PHASE 3        │◄─────────────┐
    │  Final Tuning       │              │
    │  Both Ports         │──────────────┘
    └──────────┬──────────┘   (optional)
               │
               │ Complete
               ▼
    ┌─────────────────────┐
    │  Recovery.RcvrCfg   │
    │  Then → L0          │
    └─────────────────────┘

6. TS1/TS2 Equalization Fields

Equalization Control Field

Bit	Name	Description
0	EC[0]	Phase indicator
1	EC[1]	Phase indicator
2	Reset EIEOS Interval Count	Reset count
3	Use Preset	1=Use preset, 0=Use coefficients
4	Request Equalization	Re-equalization request
5	Quiesce Guarantee	Tx guarantee during coefficient change

Transmitter Preset/Coefficient Fields

Transmitter Preset: 4-bit preset index (P0-P10)
Pre-cursor: 6-bit coefficient value
Cursor: 6-bit coefficient value
Post-cursor: 6-bit coefficient value

7. 64/128 GT/s Equalization Specifics

PAM4 Considerations

More sensitive to coefficient settings
Tighter tolerance on level spacing
Additional receiver adaptation needed

Extended Equalization

64 GT/s and 128 GT/s may require:

Longer adaptation time
More equalization iterations
Additional TS0 training
FEC training integration

TS0 Ordered Set

New ordered set for 64/128 GT/s training:

Contains PAM4-specific training patterns
Enables receiver calibration
Used during link bring-up

8. Lane Margining Integration

After equalization completes, Lane Margining can be used to verify link margin:

Tests voltage and timing margin
Validates equalization effectiveness
Identifies weak lanes
Supports proactive maintenance