Flattening Portal Bridge (FPB) Complete Guide

1. What is FPB?

What is Flattening Portal Bridge?

FPB enables a PCIe bridge to route transactions based on full Routing ID (Bus/Device/Function) or memory address ranges, bypassing traditional hierarchical bus number assignment. This supports topologies with many devices while conserving bus numbers.

The Problem

Traditional PCIe: 256 bus numbers maximum
Each bridge consumes at least one bus number
Large-scale systems (HPC, cloud) can exhaust bus space

2. FPB Concept

    Traditional Hierarchy:              FPB Topology:
    
    Bus 0                               Bus 0
      │                                   │
    Bridge (Sec=1, Sub=4)              FPB Bridge
      │                                   │
    ┌─┼─┐                              ┌──┼──┬──┬──┐
    │ │ │                              │  │  │  │  │
    B1 B2 B3                           D0 D1 D2 D3 D4
    │  │  │                            (all on Bus 1)
    D  D  D
    
    Uses 4 bus numbers                 Uses 1 bus number

3. FPB Extended Capability

Capability Structure

Offset	Register
00h	Extended Cap Header (ID = 0026h)
04h	FPB Capabilities
08h	FPB RID Vector Control 1
0Ch	FPB RID Vector Control 2
10h	FPB MEM Low Vector Control
14h	FPB MEM High Vector Control 1
18h	FPB MEM High Vector Control 2
1Ch	FPB Vector Access Control
20h	FPB Vector Access Data

4. Routing Vectors

RID Vector

Bitmask indicating which Routing IDs are behind this port

One bit per possible RID
Enables direct lookup routing

MEM Vectors

Bitmasks for memory address routing:

MEM Low: Below 4GB addresses
MEM High: Above 4GB addresses

5. Use Cases

HPC Clusters: Thousands of endpoints
Storage Arrays: Many NVMe drives
CXL Memory Pooling: Large device counts
Disaggregated Infrastructure: Composable systems