L1 PM Substates (L1.1 & L1.2)

Deep-Dive: Ultra-Low Power Link States with Common Mode Voltage Removal and Clock Gating

1. L1 PM Substates Overview

L1 PM Substates extend the basic L1 power management state with deeper low-power modes that significantly reduce power consumption when the link is idle. These substates are critical for mobile and battery-powered devices.

Power Savings Hierarchy

L0 (Active) → L0s (Standby) → L1.0 (Basic L1) → L1.1 (Low Power) → L1.2 (Ultra-Low Power)

  • L1.0: Basic L1 state - PLL can be turned off
  • L1.1: PLL off + CLKREQ# low (no clock)
  • L1.2: L1.1 + Common mode voltage removed (lowest power)

State Comparison

State PLL REFCLK Common Mode Wake Latency Power
L1.0 Off On On ~1-4 µs Medium-Low
L1.1 Off Off (CLKREQ#) On ~4-32 µs Low
L1.2 Off Off (CLKREQ#) Off ~32-100 µs Ultra-Low

2. L1.1 Substate

2.1 L1.1 Entry Conditions

L1.1 Entry Requirements: 1. Link must be in L1 state 2. CLKREQ# signal asserted (pulled low by device) 3. Both endpoints support L1.1 (L1 PM Substates Capability) 4. L1.1 enabled in L1 PM Substates Control register 5. No pending transactions Entry Sequence: ┌─────────────────────────────────────────────────────────────────────────┐ │ │ │ ┌──────────┐ ASPM L1 ┌──────────┐ CLKREQ#=0 ┌──────────┐ │ │ │ L0 │ ──────────────► │ L1.0 │ ─────────────► │ L1.1 │ │ │ │ (Active) │ (PLL runs) │(PLL off) │ (no clock) │ (Low Pwr)│ │ │ └──────────┘ └──────────┘ └──────────┘ │ │ ▲ │ │ │ │ L1.2 entry timeout │ │ │ │ ◄───────────────────────────────────────────►│ │ │ │ ▼ │ │ │ ┌──────────┐ │ │ └──────────────────────────────────────────────────│ L1.2 │ │ │ Wake event │(UltraLow)│ │ │ └──────────┘ │ └─────────────────────────────────────────────────────────────────────────┘

2.2 CLKREQ# Signaling

CLKREQ# Protocol (Active-Low, Open-Drain): Downstream Port Upstream Port (Root Port/Switch) (Endpoint/Switch) │ │ │ CLKREQ# pin │ │◄──────────────────────────────────────│ │ │ Signal States: CLKREQ# = HIGH (deasserted): Device needs reference clock CLKREQ# = LOW (asserted): Device does not need clock Electrical Requirements: • Open-drain output with weak pull-up • Maximum propagation delay: 400 ns • Must be on always-on power rail (not affected by L1.2 power removal) Timing Diagram: L0 │ L1.0 │ L1.1 │ Exit ──────────────────┼──────────────┼────────────────┼────────────── │ │ │ CLKREQ# ──────────┴──────────────┘ ┌─────────────── Entry to L1 T_POWER_OFF Wake asserts CLKREQ# │ │ │ REFCLK ████████████████████████│ │████████████████ Clock running Clock stopped Clock restarted

3. L1.2 Substate

3.1 L1.2 Entry Conditions

L1.2 is the deepest low-power substate, removing common mode voltage from the link for maximum power savings.

L1.2 Entry Requirements: All L1.1 requirements PLUS: 1. T_POWER_ON time has been communicated (via L1 PM Substates Cap) 2. Both ports support L1.2 (ASPM L1.2 Supported bit) 3. L1.2 enabled in L1 PM Substates Control register 4. L1.2 Entry Threshold condition met: LTR (Latency Tolerance Reporting) based entry: If device reports LTR value > (T_POWER_ON + T_L1.2): OK to enter L1.2 Else: Remain in L1.1 (faster exit) L1.2 Entry State Machine: ┌─────────────────────────────────────┐ │ L1.1 │ │ (Clock off, Common mode ON) │ └──────────────────┬──────────────────┘ │ │ L1.2 Entry Threshold met? │ AND T_PCLKREQ > threshold? │ ┌────────┴────────┐ │ Yes │ No ▼ ▼ ┌─────────────────┐ ┌─────────────────┐ │ L1.2.Entry │ │ Stay in L1.1 │ │ (Transitioning) │ │ (Faster wake) │ └────────┬────────┘ └─────────────────┘ │ │ Common mode voltage ramp-down │ ▼ ┌─────────────────────────────────────┐ │ L1.2.Idle │ │ (Clock off, Common mode OFF) │ │ (MINIMUM POWER STATE) │ └─────────────────────────────────────┘

3.2 Common Mode Voltage Removal

Electrical State in L1.2: Normal Operation (L0/L1.0/L1.1): ┌─────────────────────────────────────────────────────────────────┐ │ │ │ TX+ ═══════════════════════════════════════════════ RX+ │ │ │ │ │ │ │ Vcm = ~350mV (common mode) │ │ │ │ │ │ │ TX- ═══════════════════════════════════════════════ RX- │ │ │ │ Termination: 50Ω to Vcm │ └─────────────────────────────────────────────────────────────────┘ L1.2 State (Common Mode Removed): ┌─────────────────────────────────────────────────────────────────┐ │ │ │ TX+ ═══════════════════════════════════════════════ RX+ │ │ │ │ │ │ │ Vcm ≈ 0V (removed) │ │ │ │ (or floating) │ │ │ TX- ═══════════════════════════════════════════════ RX- │ │ │ │ High-impedance state - no DC current flow │ └─────────────────────────────────────────────────────────────────┘ Power Savings: • TX driver bias current: 0 mA (vs ~5-10 mA in L1.1) • RX termination current: 0 mA (vs ~3-5 mA) • Typical savings: 5-15 mW per lane

3.3 L1.2 Exit Sequence

L1.2 Exit Timing: Time Event ──── ───────────────────────────────────────────────────────────── t=0 Wake event (transaction pending OR upstream CLKREQ# deasserted) t=0 CLKREQ# asserted HIGH by device needing to exit ↓ Platform detects CLKREQ# assertion ↓ t=T1 Platform begins REFCLK startup ↓ t=T2 REFCLK stable (T_PCLKREQ elapsed) ↓ Port begins PLL lock ↓ t=T3 Common mode voltage ramp-up begins ↓ t=T4 Common mode voltage stable (T_POWER_ON elapsed) ↓ Port begins L1 exit sequence ↓ t=T5 LTSSM transitions to Recovery ↓ t=T6 Link returns to L0 Total Exit Latency Formula: T_L1.2_exit = T_PCLKREQ + T_POWER_ON + T_L1_exit Where: T_PCLKREQ = Time for REFCLK to become stable (platform dependent) T_POWER_ON = Time for common mode to stabilize (from capability) T_L1_exit = L1 to L0 transition time (from ASPM capability) Example Calculation: T_PCLKREQ = 10 µs (platform) T_POWER_ON = 40 µs (from device capability) T_L1_exit = 32 µs (from Link Capabilities) ─────────────────────────────────── Total = 82 µs L1.2 exit latency

4. Timing Parameters

4.1 L1 PM Substates Timing Registers

Parameter Register Field Unit Description
T_POWER_ON_SCALE L1 PM Substates Cap[1:0] - Scale for T_POWER_ON value (2µs, 10µs, 100µs)
T_POWER_ON_VALUE L1 PM Substates Cap[7:3] scaled Common mode restore time
T_CommonMode L1 PM Substates Control[15:8] µs Time after L1.2 entry before common mode removed
LTR_L1.2_THRESHOLD_VALUE L1 PM Substates Control 2[9:0] scaled LTR threshold for L1.2 entry
LTR_L1.2_THRESHOLD_SCALE L1 PM Substates Control 2[12:10] - Scale (1ns to 32768µs)

4.2 Scale Value Encoding

T_POWER_ON Scale (2 bits): 00b = 2 µs 01b = 10 µs 10b = 100 µs 11b = Reserved LTR Threshold Scale (3 bits): 000b = 1 ns 001b = 32 ns 010b = 1024 ns (1.024 µs) 011b = 32768 ns (32.768 µs) 100b = 1048576 ns (1.048 ms) 101b = 33554432 ns (33.554 ms) 110b-111b = Reserved Example T_POWER_ON Calculation: T_POWER_ON_SCALE = 01b (10 µs base) T_POWER_ON_VALUE = 00100b (4) T_POWER_ON = 4 × 10 µs = 40 µs

5. L1 PM Substates Extended Capability Registers

5.1 Capability Register (Offset 04h)

L1 PM Substates Capabilities Register (32 bits): ┌─────────────────────────────────────────────────────────────────────────┐ │ Bit │ Field │ Description │ ├─────┼────────────────────────────────┼─────────────────────────────────┤ │ 0 │ PCI-PM L1.2 Supported │ L1.2 via PCI-PM entry supported │ │ 1 │ PCI-PM L1.1 Supported │ L1.1 via PCI-PM entry supported │ │ 2 │ ASPM L1.2 Supported │ L1.2 via ASPM entry supported │ │ 3 │ ASPM L1.1 Supported │ L1.1 via ASPM entry supported │ │ 4 │ L1 PM Substates Supported │ Any L1 substate supported │ │ 7:5 │ Reserved │ │ │15:8 │ Port Common Mode Restore Time │ T_POWER_ON value │ │17:16│ Port T_POWER_ON Scale │ Scale for T_POWER_ON │ │23:18│ Reserved │ │ │31:24│ Port T_POWER_ON Value │ Actual T_POWER_ON value │ └─────────────────────────────────────────────────────────────────────────┘

5.2 Control Register 1 (Offset 08h)

L1 PM Substates Control 1 Register (32 bits): ┌─────────────────────────────────────────────────────────────────────────┐ │ Bit │ Field │ Description │ ├─────┼────────────────────────────────┼─────────────────────────────────┤ │ 0 │ PCI-PM L1.2 Enable │ Enable L1.2 via PCI-PM │ │ 1 │ PCI-PM L1.1 Enable │ Enable L1.1 via PCI-PM │ │ 2 │ ASPM L1.2 Enable │ Enable L1.2 via ASPM │ │ 3 │ ASPM L1.1 Enable │ Enable L1.1 via ASPM │ │ 7:4 │ Reserved │ │ │15:8 │ Common_Mode_Restore_Time │ Programmed T_CommonMode │ │29:16│ LTR_L1.2_THRESHOLD_Value │ Threshold for L1.2 entry │ │31:30│ Reserved │ │ └─────────────────────────────────────────────────────────────────────────┘

5.3 Control Register 2 (Offset 0Ch)

L1 PM Substates Control 2 Register (32 bits): ┌─────────────────────────────────────────────────────────────────────────┐ │ Bit │ Field │ Description │ ├─────┼────────────────────────────────┼─────────────────────────────────┤ │ 9:0 │ T_POWER_ON_VALUE │ Programmed power-on time │ │12:10│ T_POWER_ON_SCALE │ Scale for programmed time │ │31:13│ Reserved │ │ └─────────────────────────────────────────────────────────────────────────┘

6. Software Configuration

6.1 Enabling L1 PM Substates

Software Flow for Enabling L1 PM Substates: enable_l1_pm_substates(downstream_port, upstream_port): // Step 1: Check capability support on both ports ds_cap = config_read(downstream_port, L1PM_CAP) us_cap = config_read(upstream_port, L1PM_CAP) l1_1_supported = (ds_cap.aspm_l1_1 AND us_cap.aspm_l1_1) l1_2_supported = (ds_cap.aspm_l1_2 AND us_cap.aspm_l1_2) if NOT (l1_1_supported OR l1_2_supported): return ERROR_NOT_SUPPORTED // Step 2: Calculate common T_POWER_ON (use maximum) ds_t_power_on = calculate_t_power_on(ds_cap) us_t_power_on = calculate_t_power_on(us_cap) common_t_power_on = MAX(ds_t_power_on, us_t_power_on) // Step 3: Program Control registers ctrl1 = 0 if l1_1_supported: ctrl1 |= ASPM_L1_1_ENABLE if l1_2_supported: ctrl1 |= ASPM_L1_2_ENABLE ctrl1.common_mode_restore_time = common_t_power_on // Set LTR threshold based on expected idle patterns ctrl1.ltr_threshold = calculate_ltr_threshold(common_t_power_on) // Step 4: Write to both ports config_write(downstream_port, L1PM_CTRL1, ctrl1) config_write(upstream_port, L1PM_CTRL1, ctrl1) // Step 5: Enable ASPM L1 in Link Control register enable_aspm_l1(downstream_port) return SUCCESS

6.2 Linux Configuration

# Check L1 PM Substates capability: $ lspci -vvv -s 01:00.0 | grep -A 10 "L1 SubState" # View current L1 PM Substates settings: $ cat /sys/bus/pci/devices/0000:01:00.0/link/l1_aspm_pm # Enable L1 PM Substates via sysfs: $ echo 1 > /sys/bus/pci/devices/0000:01:00.0/link/l1_1_aspm $ echo 1 > /sys/bus/pci/devices/0000:01:00.0/link/l1_2_aspm # View current ASPM policy: $ cat /sys/module/pcie_aspm/parameters/policy # Set ASPM policy (powersave, performance, powersupersave): $ echo powersupersave > /sys/module/pcie_aspm/parameters/policy # Example lspci output: L1 SubState Cap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ Port CommonModeRestoreTime=40us Port T_POWER_ON_Scale=10us Port T_POWER_ON_Value=4us L1 SubState Ctl: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1+ T_CommonMode=40us LTR1.2_Threshold=163840ns

7. Normative Rules

L1 PM Substates Implementation Rules

  1. R1: Both link partners MUST support L1.1/L1.2 for the substate to be used.
  2. R2: CLKREQ# MUST be on an always-on power domain (not removed in L1.2).
  3. R3: T_POWER_ON advertised MUST account for worst-case common mode restore time.
  4. R4: Software MUST program identical L1 PM Substates Control values on both link partners.
  5. R5: L1.2 entry MUST NOT occur if LTR value is less than calculated exit latency.
  6. R6: Link MUST transition through L1.1 before entering L1.2.
  7. R7: ASPM L1 MUST be enabled for ASPM L1.1/L1.2 to function.
  8. R8: Devices MUST NOT enter L1.2 during Configuration or Recovery states.
  9. R9: Wake latency guarantee MUST be honored once L1.2 entry occurs.
  10. R10: Common mode voltage removal MUST NOT begin until T_CommonMode expires.