Link Training and Status State Machine: All states, substates, transitions, timeouts, and variables
The Link Training and Status State Machine (LTSSM) is the heart of PCIe Physical Layer operation. It manages link initialization, training, power management, error recovery, and link width/speed changes.
| State | Purpose | Link Status |
|---|---|---|
| Detect | Detect receiver presence | Inactive |
| Polling | Establish bit/symbol lock, lane polarity | Training |
| Configuration | Negotiate link width, assign lane numbers | Training |
| L0 | Normal operation, TLP/DLLP exchange | Active (DL_Up) |
| Recovery | Error recovery, speed/EQ changes | Temporarily Down |
| L0s | Low-latency power saving (ASPM) | Power Saving |
| L1 | Low-power state (deeper ASPM) | Power Saving |
| L2 | Very low power (aux power) | Power Down |
| Disabled | Link disabled (DPC, software) | Disabled |
| Loopback | Testing/diagnostic mode | Test |
| Hot Reset | In-band reset via TS1 | Reset |
┌─────────┐
┌─────────────│ RESET │─────────────┐
│ └────┬────┘ │
│ │ │
│ ▼ │
│ ┌──────────┐ │
│ │ DETECT │◄────────────┼───────────────┐
│ └────┬─────┘ │ │
│ │ Receiver │ │
│ │ Detected │ │
│ ▼ │ │
│ ┌──────────┐ │ │
│ │ POLLING │──────────────┤ │
│ └────┬─────┘ Timeout │ │
│ │ │ │
│ │ TS1/TS2 │ │
│ │ Exchange │ │
│ ▼ │ │
│ ┌─────────────────┐ │ │
│ │ CONFIGURATION │──────────┤ │
│ └────────┬────────┘ Timeout │ │
│ │ │ │
│ │ Width/Lane │ │
│ │ Configured │ │
│ ▼ │ │
┌──────────────┼─────────────► L0 ◄──────────────────┤ │
│ │ (Normal) │ │
│ │ │ │ │
│ ┌───────────┼────────────────┼────────────────────┼───────────┐ │
│ │ │ │ │ │ │
│ │ L0s ◄────┤ │ │ │ │
│ │ (ASPM) │ │ │ L1 ◄───┤ │
│ │ │ │ │ (ASPM) │ │
│ └───────────┤ │ │ │ │
│ │ │ └───────────┤ │
│ │ │ │ │
│ │ ▼ │ │
│ │ ┌──────────┐ │ │
│ └─────────│ RECOVERY │◄───────────────────────────┘ │
│ └────┬─────┘ │
│ │ │
│ ┌───────────────────────┼───────────────────────┐ │
│ │ │ │ │
│ ▼ ▼ ▼ │
│ DISABLED HOT RESET LOOPBACK │
│ │ │ │ │
│ └───────────────────────┴───────────────────────┴──────────────┘
│ │
│ ▼
│ ┌─────────┐
└────────────────────────────────│ L2 │
└─────────┘
The LTSSM begins in Detect after reset. This state detects the presence of a receiver on the other end of the link.
Receiver detection uses impedance measurement:
| Timer | Value | Description |
|---|---|---|
| Detect.Quiet timeout | 12ms | Wait before detection attempt |
| Detect.Active timeout | 12ms | Maximum detection time |
Polling establishes bit lock, symbol lock, and determines lane polarity inversion.
| Timer | Value |
|---|---|
| Polling.Active timeout | 24ms |
| Polling.Configuration timeout | 48ms |
Configuration negotiates the final link width and assigns lane numbers.
Both ports advertise supported widths and negotiate the maximum common width:
| Timer | Value |
|---|---|
| Configuration.Linkwidth timeout | 24ms |
| Configuration.Lanenum timeout | 2ms |
| Configuration.Idle timeout | 2ms |
L0 is the normal operational state where TLPs and DLLPs are exchanged. The link is fully active and at full bandwidth.
Recovery handles various scenarios including error recovery, speed changes, and link equalization.
For speeds of 8.0 GT/s and above, Recovery.Equalization performs link equalization:
Link is disabled by software or hardware (e.g., DPC):
In-band reset using TS1 with Hot Reset bit:
Diagnostic/test mode:
| Variable | Description |
|---|---|
| directed_speed_change | Speed change has been requested |
| upconfigure_capable | Link can increase width |
| equalization_done_8GT | 8.0 GT/s equalization completed |
| equalization_done_32GT | 32.0 GT/s equalization completed |
| equalization_done_64GT | 64.0 GT/s equalization completed |
| start_equalization_w_preset | Use preset for equalization start |
| idle_to_rlock_transitioned | Tracks Recovery.Idle to RcvrLock transitions |