4-level modulation, Gray coding, precoding, voltage levels, and error characteristics
PAM4 (Pulse Amplitude Modulation 4-Level) is a signaling technique that uses four distinct voltage levels to encode 2 bits per symbol, effectively doubling the data rate compared to NRZ (Non-Return-to-Zero) signaling at the same symbol rate.
| Characteristic | NRZ (2-Level) | PAM4 (4-Level) |
|---|---|---|
| Voltage Levels | 2 (High/Low) | 4 (L0, L1, L2, L3) |
| Bits per Symbol | 1 | 2 |
| Symbol Rate for 64 GT/s | 64 GBaud | 32 GBaud |
| Eye Height | Full swing | ~1/3 swing (3 eyes) |
| SNR Sensitivity | Lower | Higher (~9.5 dB penalty) |
| PCIe Usage | 2.5-32 GT/s | 64-128 GT/s |
At 64 GT/s and beyond, NRZ signaling at the required symbol rate faces severe channel and implementation challenges. PAM4 allows doubling the data rate while keeping the symbol rate (and channel bandwidth requirements) the same as 32 GT/s NRZ.
PAM4's ~9.5 dB SNR penalty is addressed through Forward Error Correction (FEC):
Voltage
▲
│
+V ───┼─── L3 (11) ═══════════════════════════════
│ ▲
│ │ Eye 3
│ ▼
+V/3 ──┼─── L2 (10) ═══════════════════════════════
│ ▲
│ │ Eye 2
│ ▼
-V/3 ──┼─── L1 (01) ═══════════════════════════════
│ ▲
│ │ Eye 1
│ ▼
-V ───┼─── L0 (00) ═══════════════════════════════
│
└────────────────────────────────────────────► Time
Symbol Encoding (Gray Code):
L0 = 00 (Lowest voltage)
L1 = 01
L2 = 10 ← Note: Not binary ordering!
L3 = 11 (Highest voltage)
| Level | Symbol | Gray Code | Normalized Voltage |
|---|---|---|---|
| L3 (Highest) | 3 | 11 | +1.0 (normalized) |
| L2 | 2 | 10 | +1/3 |
| L1 | 1 | 01 | -1/3 |
| L0 (Lowest) | 0 | 00 | -1.0 (normalized) |
PAM4 produces three "eyes" in the eye diagram:
Gray coding ensures that adjacent voltage levels differ by only one bit. This means a single-level error (misinterpreting L1 as L2, for example) only causes a single bit error instead of potentially two.
| Level | Binary (Wrong) | Gray Code (Correct) | Error Impact |
|---|---|---|---|
| L0 | 00 | 00 | - |
| L1 | 01 | 01 | L0↔L1: 1 bit error |
| L2 | 10 | 10 (different!) | L1↔L2: 1 bit error (Gray) vs 2 bits (binary) |
| L3 | 11 | 11 | L2↔L3: 1 bit error |
With Gray coding, the most common error type (single level slip due to noise) always results in exactly 1 bit error. Without Gray coding, L1↔L2 transitions would cause 2-bit errors (01↔10 in binary), doubling the effective bit error rate for these transitions.
Precoding is required for 32.0 GT/s and higher (including PAM4 speeds) to address Decision Feedback Equalizer (DFE) error propagation:
Precoded_Symbol = Original_Symbol XOR Previous_Precoded_Symbol
For PAM4 (2 bits per symbol):
MSB_precoded = MSB_original XOR MSB_previous_precoded
LSB_precoded = LSB_original XOR LSB_previous_precoded
At receiver (with DFE):
Original_Symbol = Received_Symbol XOR Previous_Received_Symbol
(Errors don't propagate because XOR "undoes" the DFE operation)
| Data Rate | Encoding | Precoding |
|---|---|---|
| 2.5 GT/s | 8b/10b NRZ | No |
| 5.0 GT/s | 8b/10b NRZ | No |
| 8.0 GT/s | 128b/130b NRZ | No |
| 16.0 GT/s | 128b/130b NRZ | No |
| 32.0 GT/s | 128b/130b NRZ | Yes (1b/1b) |
| 64.0 GT/s | Flit + PAM4 | Yes (1b/1b per lane) |
| 128.0 GT/s | Flit + PAM4 | Yes (1b/1b per lane) |
| Metric | Value |
|---|---|
| Pre-FEC BER (input to FEC) | ~10⁻⁴ to 10⁻⁵ |
| Post-FEC BER (output) | ≤ 10⁻¹² |
| FEC Coding Gain | ~7-8 orders of magnitude |
PCIe 6.0/7.0 uses FBER as a key metric:
PAM4 transmitters use 3-tap FIR filter for pre-emphasis:
Output(n) = C-1 × Input(n+1) + C0 × Input(n) + C+1 × Input(n-1)
Constraint: |C-1| + |C0| + |C+1| = 1 (normalized)
Voltage Level Slicer Decision
───────────── ───────────────
L3 Above TH3 → 11
─── TH3 ───
L2 TH2 to TH3 → 10
─── TH2 ───
L1 TH1 to TH2 → 01
─── TH1 ───
L0 Below TH1 → 00
PAM4 speeds require careful equalization: