LTSSM detailed transitions, Ordered Set encoding, equalization algorithms, timing specifications
┌────────────────────────────────────────────────────────────────────────────┐
│ DETECT STATE MACHINE │
└────────────────────────────────────────────────────────────────────────────┘
┌──────────────────────────────────────────┐
│ Detect.Quiet │
│ • Tx = Electrical Idle │
│ • Wait 12ms timeout OR receiver detect │
│ • Directed Speed Change flag checked │
└──────────────────────┬───────────────────┘
│
│ timeout or directed
▼
┌──────────────────────────────────────────┐
│ Detect.Active │
│ • Charge Tx to detect receiver │
│ • Measure impedance change │
│ • Detection time: ~12ms max │
└──────────────────────┬───────────────────┘
│
┌───────────────────┴───────────────────┐
│ │
Receiver Detected No Receiver
│ │
▼ ▼
┌────────────────────┐ ┌────────────────────┐
│ Polling │ │ Detect.Quiet │
│ │ │ (with backoff) │
└────────────────────┘ │ 1ms → 2ms → 4ms... │
│ (max 1 second) │
└────────────────────┘
Receiver Detection Mechanism:
• Transmitter applies voltage step
• Measures current/impedance response
• ~50Ω termination = receiver present
• High impedance = no receiver
• Multiple lanes must detect for multi-lane link
┌────────────────────────────────────────────────────────────────────────────┐
│ POLLING STATE MACHINE │
└────────────────────────────────────────────────────────────────────────────┘
┌──────────────────────────────────────┐
│ Polling.Active │
│ • Tx TS1 continuously │
│ • Rx CDR acquiring bit lock │
│ • Look for valid TS1/TS2 │
└──────────────────────┬───────────────┘
│
┌────────────────────────────┼────────────────────────────┐
│ │ │
8 TS1/TS2 received 24ms timeout Compliance bit
│ │ │
▼ ▼ ▼
┌───────────────────────┐ ┌────────────────────┐ ┌───────────────────────┐
│ Polling.Configuration │ │ Detect │ │ Polling.Compliance │
│ • Tx TS1, then TS2 │ │ │ │ • Tx Compliance │
│ • Count TS2 received │ │ │ │ Pattern │
└───────────┬───────────┘ └────────────────────┘ │ • Test/Debug mode │
│ └───────────────────────┘
│ 8 consecutive TS2 with
│ Link=PAD, any Lane
▼
┌──────────────────────────────────────┐
│ Configuration │
│ (or Polling.Speed if speed change) │
└──────────────────────────────────────┘
Key Timing:
• Polling.Active: 24ms timeout to Detect
• Polling.Configuration: 48ms timeout
• TS1/TS2: 16 symbols each @ link rate
┌────────────────────────────────────────────────────────────────────────────┐ │ CONFIGURATION STATE MACHINE │ └────────────────────────────────────────────────────────────────────────────┘ ┌─────────────────────────────────────────────────────────────────────────────┐ │ Configuration.Linkwidth.Start │ │ │ │ Downstream Port (DSP): │ │ • Transmit TS1 with Link Number = N (proposed) │ │ • Determine which lanes received valid TS1 │ │ │ │ Upstream Port (USP): │ │ • Wait for TS1 with Link Number ≠ PAD │ │ • Accept on lanes receiving same Link Number │ └─────────────────────────────────────────────────┬────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────────────────┐ │ Configuration.Linkwidth.Accept │ │ │ │ • Negotiate active lanes based on TS1 exchange │ │ • Handle lane reversal detection │ │ • Determine final link width (x1, x2, x4, x8, x16, x32) │ └─────────────────────────────────────────────────┬────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────────────────┐ │ Configuration.Lanenum.Wait │ │ │ │ • DSP: Transmit TS1 with Lane Numbers assigned │ │ • USP: Receive and verify lane numbering │ └─────────────────────────────────────────────────┬────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────────────────┐ │ Configuration.Lanenum.Accept │ │ │ │ • Both ports accept lane numbers │ │ • Transmit TS2 with configured Link# and Lane# │ └─────────────────────────────────────────────────┬────────────────────────────┘ │ │ 8 consecutive TS2 matching ▼ ┌─────────────────────────────────────────────────────────────────────────────┐ │ Configuration.Complete │ │ │ │ • Exchange final TS2 with all bits matching │ │ • Verify link/lane configuration stable │ └─────────────────────────────────────────────────┬────────────────────────────┘ │ │ 16 TS2 sent, 8 received ▼ ┌─────────────────────────────────────────────────────────────────────────────┐ │ Configuration.Idle │ │ │ │ • Transmit Idle data (or SDS for 128b/130b) │ │ • Transition to L0 │ └─────────────────────────────────────────────────┬────────────────────────────┘ │ ▼ ┌────────────────┐ │ L0 │ │ (Active State) │ └────────────────┘
TS1 Ordered Set (16 symbols) ═══════════════════════════════════════════════════════════════════════════════ ┌─────────┬────────────────────────┬─────────────────────────────────────────┐ │ Symbol │ Field Name │ Description │ ├─────────┼────────────────────────┼─────────────────────────────────────────┤ │ 0 │ COM │ K28.5 - Comma for alignment │ │ 1 │ Link Number │ PAD(K23.7) or assigned (0-255) │ │ 2 │ Lane Number │ PAD(K23.7) or assigned (0-31) │ │ 3 │ N_FTS │ Number of FTS for L0s exit (0-255) │ │ 4 │ Data Rate Identifier │ Speed capabilities and selection │ │ 5 │ Training Control │ Control bits (reset, loopback, etc.) │ │ 6-9 │ Equalization Control │ EQ presets/coefficients (Gen3+) │ │ 10-13 │ TS Identifier │ D10.2 = TS1, D5.2 = TS2 │ │ 14-15 │ Reserved │ Future use │ └─────────┴────────────────────────┴─────────────────────────────────────────┘ Data Rate Identifier (Symbol 4) Bit Definitions: Bit 7 │ Bit 6 │ Bit 5 │ Bit 4 │ Bit 3 │ Bit 2 │ Bit 1 │ Bit 0 ────────┼─────────┼─────────┼─────────┼─────────┼─────────┼─────────┼──────── Crosslnk│ Selectable│ Gen5 │ Auto │ Gen4 │ Gen3 │ Gen2 │ Gen1 Support │ De-emph │Supported│ Speed │Supported│Supported│Supported│Supported │ │ │ Change │ │ │ │ Training Control (Symbol 5) Bit Definitions: Bit 7 │ Bit 6 │ Bit 5 │ Bit 4 │ Bit 3 │ Bit 2 │ Bit 1 │ Bit 0 ────────┼─────────┼─────────┼─────────┼─────────┼─────────┼─────────┼──────── Reserved│ Reserved│ Reserved│Compliance│ Disable │Loopback │ Disable │ Hot │ │ │ Receive │Scramble │ │ Link │ Reset Equalization Control (Symbols 6-9) for Gen3+: Symbol 6: EC[7:0] - Transmitter Preset requested Symbol 7: EC[15:8] - Coefficient values Symbol 8: EC[23:16] - FS/LF (Full Swing / Low Frequency) Symbol 9: EC[31:24] - Phase / Request indicators
Transmitter Equalization - 3-Tap FIR ═══════════════════════════════════════════════════════════════════════════════ D(n+1) D(n) D(n-1) │ │ │ │ ┌────┐ │ ┌────┐ │ └──►│z^-1├───┴───►│z^-1├───┘ └─┬──┘ └─┬──┘ │ │ ┌────┴────┐ ┌────┴────┐ ┌────────┐ │ C-1 │ │ C0 │ │ C+1 │ │ (Pre) │ │ (Main) │ │ (Post) │ └────┬────┘ └────┬────┘ └────┬───┘ │ │ │ └──────┬──────┴──────┬──────┘ │ │ ▼ ▼ ┌────────────────────┐ │ Σ │ │ Tx Output │ └────────────────────┘ Equation: Tx_Out(n) = C(-1) × D(n+1) + C(0) × D(n) + C(+1) × D(n-1) Coefficients Meaning: C(-1): Pre-cursor - compensates for leading ISI C(0): Main cursor - primary signal amplitude C(+1): Post-cursor - compensates for trailing ISI Constraints: |C(-1)| + |C(0)| + |C(+1)| ≤ 1.0 (normalized) Coefficients expressed in dB relative to C(0)
| Preset | Pre-cursor (C-1) | Post-cursor (C+1) | Ratio (C-1/C+1) | Use Case |
|---|---|---|---|---|
| P0 | 0 dB (none) | -6.0 dB | 0:6 | Short channels |
| P1 | 0 dB | -3.5 dB | 0:3.5 | Low loss |
| P2 | 0 dB | -4.4 dB | 0:4.4 | Low loss |
| P3 | 0 dB | -2.5 dB | 0:2.5 | Minimal EQ |
| P4 | 0 dB | 0 dB | 0:0 | No EQ (test) |
| P5 | -1.9 dB | -4.0 dB | ~1:2 | Medium channels |
| P6 | -2.5 dB | -4.5 dB | ~1:2 | Medium channels |
| P7 | -3.5 dB | -3.5 dB | 1:1 | Balanced |
| P8 | -3.5 dB | -5.5 dB | ~1:1.5 | Long channels |
| P9 | -4.0 dB | -4.0 dB | 1:1 | High loss |
| P10 | -6.0 dB | 0 dB | 6:0 | Pre-cursor heavy |
CTLE (Continuous Time Linear Equalizer) ═══════════════════════════════════════════════════════════════════════════════ High-Pass Boost │ Rx Input ──────►┌───────────────┼───────────────┐──────► To DFE │ │ │ │ ┌──────────▼──────────┐ │ │ │ │ │ │ │ Analog Filter │ │ │ │ (High-frequency │ │ │ │ boost) │ │ │ │ │ │ │ └─────────────────────┘ │ │ │ └───────────────────────────────┘ Transfer Function: H(s) = (1 + s/ωz) / (1 + s/ωp) ωz: Zero frequency (sets boost start) ωp: Pole frequency (sets boost end) Boost at Nyquist = 6-12 dB typical DFE (Decision Feedback Equalizer) ═══════════════════════════════════════════════════════════════════════════════ ┌─────┐ From CTLE ───►(+)────►│Slicer│────┬────► Data Out │ └─────┘ │ │ │ │ ┌─────────────┴─────────────┐ │ │ │ │ ▼ ▼ │ ┌────┐ ┌────┐ ┌────┐ ┌────┐ │ │H(1)│◄───│z^-1│◄───│H(2)│◄─│z^-1│◄── ... │ └──┬─┘ └────┘ └──┬─┘ └────┘ │ │ │ │ └─────────┬─────────┘ │ │ └───────────────┘ (subtract ISI) DFE Taps: Tap 1 (H1): Cancels 1-UI ISI Tap 2 (H2): Cancels 2-UI ISI ...up to 5+ taps for severe channels Advantage: DFE doesn't amplify noise (unlike CTLE) Uses decisions (0/1) not analog signal
Transmitter and Receiver clocks can differ by ±300 ppm. At 32 GT/s, this equals ~9600 bits/second drift. Without SKP compensation, the elastic buffer would overflow or underflow within milliseconds.
SKP Scheduling (8b/10b Mode - Gen1/2) ═══════════════════════════════════════════════════════════════════════════════ SKP OS Format: COM + SKP + SKP + SKP (4 symbols) Scheduling Interval: • Minimum: 1180 symbols between SKP OS • Maximum: 1538 symbols between SKP OS • Typical: ~1300 symbols Timing at 2.5 GT/s: 1300 symbols × 4ns/symbol = 5.2 μs interval SKP Scheduling (128b/130b Mode - Gen3/4/5) ═══════════════════════════════════════════════════════════════════════════════ SKP_OS is a special Ordered Set Block (sync header = 10) Scheduling Interval: • Nominal: Every 370 blocks • 370 × 130 bits = 48,100 bits between SKP_OS Timing at 8 GT/s: 48,100 bits / 8 Gbps = 6.0 μs interval Timing at 32 GT/s: 48,100 bits / 32 Gbps = 1.5 μs interval Elastic Buffer Operation ═══════════════════════════════════════════════════════════════════════════════ ┌─────────────────────────────────────┐ From CDR ────────►│ Elastic Buffer │────────► To Decoder │ (FIFO) │ │ │ │ ┌───┬───┬───┬───┬───┬───┬───┬───┐ │ │ │ │ │ █ │ █ │ █ │ │ │ │ │ ◄── Half full (nominal) │ └───┴───┴───┴───┴───┴───┴───┴───┘ │ │ │ │ Buffer too full: REMOVE SKP │ │ Buffer too empty: ADD SKP │ └─────────────────────────────────────┘ Compensation Range: ±300 ppm × data rate = bits/second to compensate SKP insertion/deletion absorbs this drift Transparent to upper layers (SKP has no data meaning)
Electrical Idle States ═══════════════════════════════════════════════════════════════════════════════ Definition: Electrical Idle = Transmitter driving common-mode voltage (no differential signaling) Detection: Receiver detects Electrical Idle when: • Differential voltage < EI threshold (~65-175 mV) • For specified duration (EI detect time) Entry Signaling (EIOS): 8b/10b: COM + IDL + IDL + IDL 128b/130b: EIOS pattern in OS block After EIOS, transmitter drives Electrical Idle Exit Signaling (EIEOS): Pattern: Alternating 00h/FFh creates detectable tone Duration: 16 symbols minimum Purpose: • Wake up receiver CDR • Re-establish bit lock • Followed by TS1/TS2 or FTS Electrical Idle Timing ═══════════════════════════════════════════════════════════════════════════════ ┌─────────────────────────────────────────────────────────────────────────┐ │ │ │ Normal │ Electrical Idle │ Exit Sequence │ │ Data │ (Low Power) │ │ │ │ │ │ │ ────────── │ ───────────────────────────── │ ~~~~~~~~ │ │ EIOS → │ Common Mode │ EIEOS → TS1/FTS │ │ │ │ │ └─────────────────────────────────────────────────────────────────────────┘ │ │ │ │◄───── T_EI_min ────►│◄────── Variable ────────────►│ │ │ │ T_EI_min: Minimum time in EI before exit allowed Varies by L-state (L0s: fast, L1: longer, L2: longest)
| Parameter | Gen1-2 | Gen3 | Gen4 | Gen5 | Gen6-7 |
|---|---|---|---|---|---|
| Unit Interval (UI) | 400/200 ps | 125 ps | 62.5 ps | 31.25 ps | 15.625/7.8125 ps |
| Detect Timeout | 12 ms | ||||
| Polling Timeout | 24 ms | ||||
| Configuration Timeout | 24 ms (per sub-state) | ||||
| L0s Exit Latency | N_FTS × UI + overhead (< 1 μs typical) | ||||
| L1 Exit Latency | 2-64 μs (advertised in capability) | ||||
| Recovery Timeout | 24 ms | ||||