Dynamic Base Address Register sizing for improved GPU performance
Resizable BAR allows the system to dynamically negotiate BAR sizes with PCIe devices. Instead of fixed BAR sizes (e.g., 256MB), devices can expose their full memory (e.g., 16GB GPU VRAM) for direct CPU access.
Traditional (Fixed 256MB BAR):
┌──────────────────────────────────────────────────────────────┐
│ GPU VRAM (16 GB) │
├──────────┬───────────────────────────────────────────────────┤
│ 256MB │ Rest of VRAM not directly addressable │
│ Window │ (requires driver paging) │
└──────────┴───────────────────────────────────────────────────┘
Resizable BAR (Full 16GB BAR):
┌──────────────────────────────────────────────────────────────┐
│ GPU VRAM (16 GB) - Fully addressable by CPU │
│ │
│ ████████████████████████████████████████████████████████████ │
└──────────────────────────────────────────────────────────────┘
| Offset | Register | Description |
|---|---|---|
| 00h | Extended Cap Header | ID = 0015h |
| 04h | Capability Register (BAR 0) | Supported sizes bitmap |
| 08h | Control Register (BAR 0) | Selected size |
| 0Ch+ | Additional BAR entries | For each resizable BAR |
Resizable BAR Capability Register (32 bits):
┌──────────────────────────────────────────────────────────────┐
│ Bits 31:4: Supported Sizes Bitmap │
│ Bit 4 = 1MB supported │
│ Bit 5 = 2MB supported │
│ Bit 6 = 4MB supported │
│ ... │
│ Bit 23 = 512GB supported │
│ Bit 24-31 = Reserved │
├──────────────────────────────────────────────────────────────┤
│ Bits 3:0: Reserved │
└──────────────────────────────────────────────────────────────┘
Size Encoding:
Bit n → Size = 2^(n+20) bytes = 2^n MB
Examples:
- Bit 4 (n=4): 2^4 MB = 16 MB
- Bit 10 (n=10): 2^10 MB = 1 GB
- Bit 14 (n=14): 2^14 MB = 16 GB
Resizable BAR Control Register (32 bits):
┌──────────────────────────────────────────────────────────────┐
│ Bits 12:8: BAR Size │
│ Encoded as: Size = 2^(value+20) bytes │
│ Value 0 = 1 MB │
│ Value 4 = 16 MB │
│ Value 10 = 1 GB │
│ Value 14 = 16 GB │
├──────────────────────────────────────────────────────────────┤
│ Bits 7:5: Number of Resizable BARs │
├──────────────────────────────────────────────────────────────┤
│ Bits 2:0: BAR Index (which BAR this applies to) │
└──────────────────────────────────────────────────────────────┘
SR-IOV Virtual Functions can also use resizable BAR:
# Check Resizable BAR support
lspci -vvv -s 01:00.0 | grep -A5 "Resizable BAR"
# View current BAR sizes
lspci -vvv -s 01:00.0 | grep "Region"
# Enable (kernel parameter)
pci=realloc