SIGNAL INTEGRITY

Retimers Complete Guide

Signal regeneration, protocol tunneling, and extended reach for PCIe links

1. What are Retimers?

What is a Retimer?

Retimers are active devices in a PCIe link that receive, retime, and retransmit signals. They regenerate the signal with fresh timing, extending link reach and improving signal integrity. Unlike repeaters, retimers understand PCIe protocol and participate in link training.

Retimer vs Redriver

Feature Redriver Retimer
Signal Processing Amplification, EQ Full CDR, regeneration
Protocol Awareness None (analog) Full PCIe protocol
Link Training Transparent Participates (pseudo-port)
Jitter Passes through Cleaned (retimed)
Latency ~100 ps ~4-8 ns per retimer
Max per Link 1-2 Up to 2
Speed Support Limited (< 16 GT/s) All speeds

2. Why Retimers?

Why use Retimers?

At high data rates (32/64/128 GT/s), channel loss becomes severe. Retimers regenerate the signal, enabling longer traces, cables, and connectors that would otherwise cause link failures.

Channel Loss Problem

    Signal Quality vs Distance (without retimer):
    
    32 GT/s:  ████████████░░░░░░░░  (~12 inches max)
    64 GT/s:  ████████░░░░░░░░░░░░  (~8 inches max)
    128 GT/s: █████░░░░░░░░░░░░░░░  (~6 inches max)
    
    With 1 Retimer (2 shorter segments):
    
    32 GT/s:  ████████████ + ████████████  (~24 inches total)
    64 GT/s:  ████████ + ████████          (~16 inches total)
    128 GT/s: █████ + █████                (~12 inches total)

Use Cases

3. Retimer Architecture

Retimer Position in Link

    No Retimer:
    ┌─────────────┐                              ┌─────────────┐
    │  Upstream   │══════════════════════════════│ Downstream  │
    │   Port      │          Channel             │    Port     │
    └─────────────┘                              └─────────────┘
    
    With 1 Retimer:
    ┌─────────────┐           ┌─────────┐           ┌─────────────┐
    │  Upstream   │═══════════│ Retimer │═══════════│ Downstream  │
    │   Port      │  Link A   │ (Retime)│  Link B   │    Port     │
    └─────────────┘           └─────────┘           └─────────────┘
    
    With 2 Retimers (max):
    ┌─────────────┐      ┌─────────┐      ┌─────────┐      ┌─────────────┐
    │  Upstream   │══════│Retimer 1│══════│Retimer 2│══════│ Downstream  │
    │   Port      │Link A│         │Link B│         │Link C│    Port     │
    └─────────────┘      └─────────┘      └─────────┘      └─────────────┘

Retimer Internal Structure

                          ┌─────────────────────────────────────┐
                          │            RETIMER                  │
                          │                                     │
    Upstream     ────────►│  Rx      CDR      Tx    ────────►  Downstream
    Signal               │  EQ   ─────────►   EQ               Signal
                          │       Retiming                      │
                          │                                     │
    Upstream     ◄────────│  Tx      CDR      Rx    ◄────────  Downstream
    Signal               │  EQ   ◄─────────   EQ               Signal
                          │       Retiming                      │
                          │                                     │
                          │   ┌─────────────────────┐           │
                          │   │  Protocol Logic     │           │
                          │   │  - LTSSM State      │           │
                          │   │  - Ordered Sets     │           │
                          │   │  - Lane Margining   │           │
                          │   └─────────────────────┘           │
                          └─────────────────────────────────────┘

4. Retimer Link Training

LTSSM Participation

Retimers participate in link training as "pseudo-ports." They have their own LTSSM that coordinates with upstream and downstream endpoints.

Training Sequence

    Upstream          Retimer           Downstream
    (DSP)            (Pseudo)              (USP)
       │                 │                   │
       │──── TS1 ────────►│                   │
       │                 │──── TS1 ──────────►│
       │                 │                   │
       │                 │◄─── TS1 ───────────│
       │◄─── TS1 ────────│                   │
       │                 │                   │
       │──── TS2 ────────►│                   │
       │                 │──── TS2 ──────────►│
       │                 │                   │
       │                 │◄─── TS2 ───────────│
       │◄─── TS2 ────────│                   │
       │                 │                   │
       │═══════ L0 (Data) ═══════════════════│

Speed Negotiation

5. Equalization with Retimers

Per-Segment Equalization

With retimers, equalization happens independently on each segment. This allows optimization for each channel's characteristics.

    Without Retimer (one long channel):
    
    DSP ════════════════════════════════════════════════════ USP
           One EQ setting must work for entire channel
           (often impossible at 64+ GT/s)
    
    With Retimer (two shorter channels):
    
    DSP ═══════════════ Retimer ═══════════════ USP
          Segment A         │        Segment B
          EQ optimized      │        EQ optimized
          for A             │        for B

Equalization Process

  1. DSP equalizes with Retimer (Segment A)
  2. Retimer equalizes with USP (Segment B)
  3. Each segment achieves optimal EQ independently
  4. Overall link benefits from both optimizations

6. Retimer Modes

Protocol Transparent Mode

Protocol Tunneling Mode

7. Retimer Extended Capability

Retimer Capability Structure

Offset Register Description
00h Extended Cap Header ID = 0027h
04h Retimer Capability Supported speeds, features
08h Retimer Control Enable, mode selection
0Ch Retimer Status Current state

8. Lane Margining with Retimers

Lane Margining can test each segment independently:

Important

Each retimer adds latency (~4-8 ns). Maximum of 2 retimers allowed per link to keep latency bounded.

9. System Design Considerations

Retimer Design Rules

  1. Maximum 2 retimers per link
  2. Each retimer adds ~4-8 ns latency
  3. Retimer must support all target speeds
  4. Power: 1-3W per retimer (varies by speed)
  5. Place retimer to equalize segment lengths
  6. Consider thermal management

When to Use Retimers