TLP Types Complete Reference

1. TLP Type Encoding

Format and Type Fields

    TLP Header DW0 (Byte 0):
    ┌─────────────────────────────────────────────────────────────────┐
    │ Bit 7  │ Bit 6  │ Bit 5  │ Bit 4  │ Bit 3  │ Bit 2  │ Bit 1  │ Bit 0  │
    │ Fmt[1] │ Fmt[0] │ Type[4]│ Type[3]│ Type[2]│ Type[1]│ Type[0]│   T9   │
    └─────────────────────────────────────────────────────────────────┘
    
    Fmt[2:0] (including bit from elsewhere):
    00 = 3DW header, no data
    01 = 4DW header, no data
    10 = 3DW header, with data
    11 = 4DW header, with data
    
    Type[4:0] + Fmt determines full TLP type

Complete TLP Type Matrix

Fmt	Type[4:0]	TLP	Description	Class
00	0 0000	MRd	Memory Read (32-bit)	Non-Posted
01	0 0000	MRd	Memory Read (64-bit)	Non-Posted
00	0 0001	MRdLk	Memory Read Locked (32-bit)	Non-Posted
01	0 0001	MRdLk	Memory Read Locked (64-bit)	Non-Posted
10	0 0000	MWr	Memory Write (32-bit)	Posted
11	0 0000	MWr	Memory Write (64-bit)	Posted
00	0 0010	IORd	I/O Read	Non-Posted
10	0 0010	IOWr	I/O Write	Non-Posted
00	0 0100	CfgRd0	Config Read Type 0	Non-Posted
10	0 0100	CfgWr0	Config Write Type 0	Non-Posted
00	0 0101	CfgRd1	Config Read Type 1	Non-Posted
10	0 0101	CfgWr1	Config Write Type 1	Non-Posted
00	1 0r00	Msg	Message (various)	Posted
10	1 0r00	MsgD	Message with Data	Posted
00	0 1010	Cpl	Completion (no data)	Completion
10	0 1010	CplD	Completion with Data	Completion
00	0 1011	CplLk	Completion Locked (no data)	Completion
10	0 1011	CplDLk	Completion Locked with Data	Completion

2. Memory Transactions

Memory Read (MRd)

What: Request to read data from memory address

When: Device wants to read system memory (DMA read)

Where: Any memory-mapped region

Why: Fetch data for processing

Uses Non-Posted credits
Requires completion(s) with data
Max Read Request Size limits request

Memory Write (MWr)

What: Write data to memory address

When: Device wants to write to system memory (DMA write)

Where: Any memory-mapped region

Why: Store computed results, transfer data

Uses Posted credits
No completion returned
Max Payload Size limits data

Memory Read Locked (MRdLk) - Legacy

What: Locked memory read for RMW sequences

When: Legacy atomic operations

Why: Deprecated - use AtomicOps instead

Locks bus during operation
Severe performance impact
Blocked by many switches/RCs

3. Atomic Operations

Fmt	Type	Operation	Operand Size
01	0 1100	FetchAdd (32-bit)	32 bits
11	0 1100	FetchAdd (64-bit)	64 bits
01	0 1101	Swap (32-bit)	32 bits
11	0 1101	Swap (64-bit)	64 bits
01	0 1110	CAS (32-bit)	64 bits (cmp + swp)
11	0 1110	CAS (64-bit)	128 bits (cmp + swp)
11	0 1111	CAS (128-bit)	256 bits (cmp + swp)

AtomicOp Use Cases

FetchAdd: Counters, reference counting, queue indices
Swap: Spinlocks, flag updates
CAS: Lock-free data structures, state machines

4. Configuration Transactions

Configuration Type 0 (CfgRd0/CfgWr0)

What: Read/write to device's configuration space

When: Device enumeration, driver configuration

Where: Terminates at target device

Used when target is directly downstream
Contains Device/Function number
Register address in lower bits

Configuration Type 1 (CfgRd1/CfgWr1)

What: Configuration transaction to be routed

When: Accessing devices behind bridges

Where: Converted to Type 0 at target bridge

Contains Bus/Device/Function
Bridges convert Type 1 → Type 0

Config Space Addressing

    Type 0 Address Format:
    ┌─────────────────────────────────────────────────────────────────┐
    │ 31:12  │ 11:8       │ 7:2              │  1:0  │
    │ Rsvd   │ Ext Reg    │ Register Number  │  00   │
    └─────────────────────────────────────────────────────────────────┘
    
    Type 1 Address Format:
    ┌─────────────────────────────────────────────────────────────────┐
    │ 31:24  │ 23:16  │ 15:11   │ 10:8      │ 7:2    │ 1:0 │
    │ Rsvd   │ Bus    │ Device  │ Function  │ Reg    │ 01  │
    └─────────────────────────────────────────────────────────────────┘

5. I/O Transactions

I/O Read/Write (IORd/IOWr)

What: Access legacy I/O port space

When: Legacy device compatibility

Why: Support older devices without MMIO

Limited to 32-bit address (64KB space)
Both use Non-Posted credits
Strongly ordered (no relaxed ordering)
Deprecated - use MMIO when possible

6. Completion Transactions

Completion (Cpl)

What: Response without data

When: I/O Write, Config Write acknowledgment

Contains status (SC, UR, CRS, CA)
Uses Completion credits

Completion with Data (CplD)

What: Response containing requested data

When: Memory Read, Config Read, AtomicOp

May require multiple CplDs for large reads
Read Completion Boundary (RCB) affects splitting

Completion Status Codes

Code	Status	Meaning
000	SC (Successful Completion)	Request completed successfully
001	UR (Unsupported Request)	Request not supported
010	CRS (Config Retry Status)	Device not ready, retry later
100	CA (Completer Abort)	Completer cannot complete

7. Message Transactions

Message Routing Types

r[2:0]	Routing	Description
000	Routed to Root Complex	Goes to RC
001	Routed by Address	Uses address field
010	Routed by ID	Uses Bus/Dev/Func
011	Broadcast from RC	RC broadcasts downstream
100	Local	Terminates at receiver
101	Gathered to RC	Aggregated upstream

Common Message Types

Assert_INTx: Legacy interrupt assertion
Deassert_INTx: Legacy interrupt deassertion
PM_Active_State_Nak: Power management
PM_PME: Power Management Event
Error Messages: ERR_COR, ERR_NONFATAL, ERR_FATAL
Vendor Defined: Vendor-specific messages
LTR: Latency Tolerance Reporting

8. PCIe 6.0+ TLP Types

Unordered I/O (UIO) TLPs

TLP Type	Description	Credit Class
UIOMRd	UIO Memory Read	Non-Posted
UIOMWr	UIO Memory Write	Posted or Non-Posted
UIORdCpl	UIO Read Completion	Completion
UIORdCplD	UIO Read Completion with Data	Completion
UIOWrCpl	UIO Write Completion	Completion

Deferrable Memory (DfMRd)

What: Memory read that can be deferred by completer
When: Accessing CXL or other high-latency memory
Why: Avoid blocking link while waiting
Returns placeholder completion immediately
Actual data delivered later via DfCplD

9. TLP Prefixes

Local TLP Prefix

Processed and removed at each link endpoint. Contains per-link information.

PASID TLP Prefix (Process Address Space ID)
Vendor-specific local prefix

End-to-End TLP Prefix

Preserved from requester to completer. Contains end-to-end information.

IDE TLP Prefix (encryption/integrity)
TPH (TLP Processing Hints)
Vendor-specific E2E prefix

TLP Prefix Format

    TLP with Prefix:
    ┌──────────────────────────────────────────────────────────────┐
    │ E2E Prefix 0 │ E2E Prefix 1 │ Local Prefix │ TLP Header ... │
    │    (4 DW)    │    (4 DW)    │    (1 DW)    │                │
    └──────────────────────────────────────────────────────────────┘
    
    Prefix First DW:
    ┌──────────────────────────────────────────────────────────────┐
    │ Fmt=100/101 │ Type[4:0]  │ Prefix-specific content          │
    │   E2E/Local │            │                                  │
    └──────────────────────────────────────────────────────────────┘

10. TLP Application Matrix

Use Case to TLP Mapping

Use Case	TLP Types Used	Notes
DMA Read	MRd → CplD	Device reads system memory
DMA Write	MWr	Device writes system memory
MMIO Read	MRd → CplD	CPU reads device register
MMIO Write	MWr	CPU writes device register
Device Enumeration	CfgRd0/1 → CplD	Read config space
MSI/MSI-X	MWr	Interrupt via memory write
Lock-free Queue	AtomicOp (CAS) → CplD	Compare-and-swap
Reference Count	AtomicOp (FetchAdd) → CplD	Atomic increment
Power Event	Msg (PM_PME)	Wake signal
Error Report	Msg (ERR_*)	Error notification
CXL Memory	DfMRd → DfCplD	Deferrable for latency hiding