Traffic Classes, Virtual Channels, arbitration algorithms (WRR, strict), and port arbitration
Traffic Classes (TC) are 3-bit labels (TC0-TC7) in TLP headers that indicate the priority or type of traffic. They enable differentiated QoS handling throughout the PCIe fabric.
| TC | Description | Typical Use |
|---|---|---|
| TC0 | Best Effort (Default) | General traffic |
| TC1 | Best Effort (Low Priority) | Background traffic |
| TC2-TC3 | Best Effort (Higher Priority) | Elevated priority |
| TC4-TC5 | Video/Streaming | Low latency traffic |
| TC6 | Controlled Load | Guaranteed bandwidth |
| TC7 | Network Control | Highest priority |
Virtual Channels (VC) are independent logical transmission pathways within a PCIe link. Each VC has separate flow control and buffering, enabling traffic isolation and differentiated QoS.
Traffic Classes Virtual Channels
TC0 ─────────────────────► VC0 (always)
TC1 ─────────────────┬───► VC0 (default)
TC2 ────────────────┬┤
TC3 ───────────────┬┤├───► VC1 (optional)
TC4 ──────────────┬┤├┤
TC5 ─────────────┬┤├┤├───► VC2 (optional)
TC6 ────────────┬┤├┤├┤
TC7 ───────────┬┤├┤├┤├───► VC7 (optional)
│││││││
└┴┴┴┴┴┴───► TC/VC Mapping Table
Configuration determines which TCs map to which VCs
TC0 MUST always map to VC0
Other TCs can map to any enabled VC
┌────────────────────────────────────────────────────────┐
│ PORT ARBITER │
│ │
│ VC0 ──┐ │
│ ├──► Port Arbitration ──► Link Egress │
│ VC1 ──┤ │
│ │ │
│ ... │ │
│ │ │
│ VC7 ──┘ │
│ │
└────────────────────────────────────────────────────────┘
▲
│
┌────────────────────────────────────────────────────────┐
│ VC ARBITER (per VC) │
│ │
│ Port A (TC x) ──┐ │
│ ├──► VC Arbitration ──► VC Queue │
│ Port B (TC y) ──┤ │
│ │ │
│ Port C (TC z) ──┘ │
│ │
└────────────────────────────────────────────────────────┘
Level 1: VC Arbitration - selects TLP within each VC
Level 2: Port Arbitration - selects which VC to transmit
Arbitrates among TLPs within a single VC from multiple ingress ports:
Arbitrates among VCs for access to the link egress:
WRR Example (Weights: VC0=4, VC1=2, VC2=1, VC3=1)
Round 1: VC0, VC0, VC0, VC0
Round 2: VC1, VC1
Round 3: VC2
Round 4: VC3
(repeat)
Bandwidth: VC0=50%, VC1=25%, VC2=12.5%, VC3=12.5%
| Offset | Register |
|---|---|
| 00h | Extended Capability Header (ID = 0002h) |
| 04h | Port VC Capability Register 1 |
| 08h | Port VC Capability Register 2 |
| 0Ch | Port VC Control Register |
| 0Eh | Port VC Status Register |
| 10h+ | VC Resource Capability/Control/Status (per VC) |
Time-sensitive traffic requiring guaranteed bandwidth and bounded latency:
TC/VC mapping must be consistent across the entire path from Requester to Completer. Inconsistent mapping can cause traffic to use different VCs at different points, breaking QoS guarantees.