Configuration Space
Every PCIe function has a configuration space that software uses for discovery and setup.
Configuration Space Layout
- Bytes 0-63: PCI-compatible header (Type 0 or Type 1)
- Bytes 64-255: PCI Capabilities
- Bytes 256-4095: PCIe Extended Capabilities
Type 0 Configuration Header (Endpoints)
| Offset | Register | Size |
|---|---|---|
| 00h | Vendor ID | 16 bits |
| 02h | Device ID | 16 bits |
| 04h | Command | 16 bits |
| 06h | Status | 16 bits |
| 08h | Revision ID | 8 bits |
| 09h | Class Code | 24 bits |
| 0Ch | Cache Line Size | 8 bits |
| 0Dh | Latency Timer | 8 bits |
| 0Eh | Header Type | 8 bits |
| 0Fh | BIST | 8 bits |
| 10h-24h | Base Address Registers (BAR0-5) | 6 × 32 bits |
| 2Ch | Subsystem Vendor ID | 16 bits |
| 2Eh | Subsystem ID | 16 bits |
| 30h | Expansion ROM Base | 32 bits |
| 34h | Capabilities Pointer | 8 bits |
| 3Ch | Interrupt Line | 8 bits |
| 3Dh | Interrupt Pin | 8 bits |
Type 1 Configuration Header (Bridges)
Type 1 headers are used by switches and bridges to define routing:
- Primary, Secondary, Subordinate Bus Numbers
- Memory and I/O routing windows
- Bridge Control register
Base Address Registers (BARs)
BARs define memory and I/O regions that the device exposes:
Bit 0: Memory (0) or I/O (1)
For Memory:
Bits [2:1]: Type (00=32-bit, 10=64-bit)
Bit 3: Prefetchable
Bits [31:4]: Base Address (16-byte aligned min)
BAR Sizing Algorithm
- Write all 1s to BAR
- Read back the value
- Mask type bits and invert
- Add 1 to get size
PCI Capabilities
Capabilities are linked list structures starting at Capabilities Pointer (offset 34h):
| Cap ID | Capability | Required? |
|---|---|---|
| 01h | Power Management | Yes |
| 05h | MSI | MSI or MSI-X |
| 10h | PCI Express | Yes |
| 11h | MSI-X | MSI or MSI-X |
PCIe Extended Capabilities
Extended capabilities start at offset 100h and include:
- AER (0001h): Advanced Error Reporting
- VC (0002h): Virtual Channel
- Serial Number (0003h): Device Serial Number
- Power Budgeting (0004h)
- ACS (000Dh): Access Control Services
- ARI (000Eh): Alternative Routing-ID
- SR-IOV (0010h): Single Root I/O Virtualization
- LTR (0018h): Latency Tolerance Reporting
- L1 PM Substates (001Eh)
- Secondary PCIe (0019h): For 8+ GT/s
- Data Link Feature (0025h)
- Physical Layer 16/32/64/128 GT/s
- IDE (0030h): Integrity and Data Encryption
Enhanced Configuration Access Mechanism (ECAM)
ECAM provides memory-mapped access to all 4KB of configuration space:
Address = ECAM_Base + (Bus << 20) + (Device << 15) + (Function << 12) + Register
Example: Bus 0, Device 1, Function 0, Register 0x10
Address = ECAM_Base + 0x00008010