Chapter 8: Electrical Specifications

Signaling, Impedance, and PHY Requirements

Signaling Overview

PCIe uses differential signaling for noise immunity and high-speed data transmission.

Signaling Methods by Generation

  • Gen1-5 (2.5-32 GT/s): NRZ (Non-Return to Zero) - 2 voltage levels
  • Gen6-7 (64-128 GT/s): PAM4 - 4 voltage levels

NRZ Signaling (Gen1-5)

ParameterGen1-2Gen3-5
Differential Swing (Vp-p)800-1200 mV800-1300 mV
Common Mode Voltage0 V (AC coupled)0 V (AC coupled)
Encoding8b/10b128b/130b
Unit Interval (UI)400ps / 200ps125ps → 31.25ps

PAM4 Signaling (Gen6-7)

PAM4 transmits 2 bits per symbol using 4 amplitude levels:

PAM4 Eye Diagram Concept Time V Level 0 (00) Level 1 (01) Level 2 (10) Level 3 (11)
Parameter64 GT/s (Gen6)128 GT/s (Gen7)
Symbol Rate32 GBaud64 GBaud
Bits per Symbol22
Unit Interval31.25 ps15.625 ps
FECRequiredRequired
Gray CodingYesYes

PAM4 Challenges

With 3 eyes instead of 1, PAM4 has ~9.5 dB less SNR margin compared to NRZ. This requires sophisticated FEC (Forward Error Correction) and equalization.

Impedance Requirements

Link Equalization

High-speed PCIe requires equalization to compensate for channel loss:

Transmitter Equalization (Tx EQ)

Receiver Equalization

Connectors and Form Factors

Form FactorLanesUse Case
CEM (Add-in Card)x1, x4, x8, x16Desktop, Server
M.2x1, x2, x4SSDs, WiFi
U.2 / U.3x4Enterprise SSDs
OCuLinkx4, x8External PCIe
EDSFFx4, x8Enterprise SSDs

Retimers

Retimers regenerate signals for extended reach: