FLIT MODE ESSENTIAL

FEC (Forward Error Correction)

Reed-Solomon FEC, 3-way interleaving, error correction capability, and Flit integration

1. What is FEC?

What is Forward Error Correction?

FEC (Forward Error Correction) is an error correction technique that adds redundant data (parity) to transmitted information, enabling the receiver to detect and correct errors without retransmission. PCIe 6.0/7.0 Flit Mode uses Reed-Solomon FEC.

Why FEC in PCIe 6.0/7.0?

2. Reed-Solomon FEC Overview

Reed-Solomon Characteristics

RS Code Notation

Reed-Solomon RS(n, k)

n = total symbols (data + parity) k = data symbols n - k = parity symbols t = (n - k) / 2 = correctable symbol errors PCIe FEC uses RS(150, 148): n = 150 bytes total k = 148 bytes data n - k = 2 bytes parity t = 1 byte correction capability per codeword

3. PCIe FEC Structure

3-Way Interleaved FEC

PCIe uses three interleaved RS codewords per Flit:

    256-Byte Flit Structure with FEC
    
    ┌──────────────────────────────────────────────────────────────┐
    │                        256 Bytes                              │
    ├──────────────────────────────┬─────────────┬─────────────────┤
    │      TLP Data (236 bytes)    │ DLP (6B)    │   CRC (8B)      │
    │                              │             │   FEC ECC (6B)  │
    └──────────────────────────────┴─────────────┴─────────────────┘
    
    FEC Coverage (250 bytes → 3 codewords):
    
    Codeword 0: Bytes 0, 3, 6, 9, ... (every 3rd byte starting at 0)
    Codeword 1: Bytes 1, 4, 7, 10, ... (every 3rd byte starting at 1)
    Codeword 2: Bytes 2, 5, 8, 11, ... (every 3rd byte starting at 2)
    
    Each codeword: ~83 data bytes + 2 parity bytes = 85 bytes
    Total parity: 6 bytes (2 per codeword)

Interleaving Benefit

4. FEC Encoding

Encoding Process

  1. Assemble Flit (TLP data, DLP, CRC)
  2. Interleave bytes into 3 groups
  3. Calculate RS parity for each group
  4. Append 2-byte parity to each codeword
  5. De-interleave to form final Flit with ECC
  6. Transmit Flit

Interleaving Pattern

    Input bytes: B0, B1, B2, B3, B4, B5, B6, B7, B8, ...
    
    Codeword 0: B0, B3, B6, B9, ... + P0a, P0b
    Codeword 1: B1, B4, B7, B10, ... + P1a, P1b
    Codeword 2: B2, B5, B8, B11, ... + P2a, P2b
    
    Output (interleaved parity):
    ... B246, B247, B248, B249, P0a, P1a, P2a, P0b, P1b, P2b
                               └─────── 6 ECC bytes ───────┘

5. FEC Decoding

Decoding Process

  1. Receive Flit
  2. Separate bytes into 3 interleaved groups
  3. For each codeword:
    • Calculate syndrome
    • If syndrome ≠ 0, error detected
    • Locate error position
    • Calculate error value
    • Correct byte
  4. De-interleave corrected data
  5. Verify CRC (additional check)

Syndrome Calculation

Syndrome indicates presence and location of errors:

6. Error Correction Capability

Single Codeword Capability

Flit-Level Capability (with interleaving)

Error Pattern Result
1 byte error anywhere Corrected
2 byte burst error Corrected
3 byte burst error Corrected
3 scattered errors (1 per codeword) Corrected
4+ byte burst error Detected (CRC fails)
2 errors in same codeword Detected (not corrected)

BER Improvement

Effective BER Improvement

Pre-FEC BER: ~10⁻⁴ to 10⁻⁵ (typical for PAM4) Post-FEC BER: < 10⁻¹² (specification target) Coding Gain: ~7-8 orders of magnitude improvement

7. FEC Latency

Latency Components

Latency vs Retry

Approach Latency Bandwidth Impact
FEC Correction ~20 ns None (inline)
Retry (ACK/NAK) ~1-2 μs Replay buffer overhead
FEC + CRC + Retry

FEC corrects most errors. CRC detects uncorrectable errors. Retry handles uncorrectable cases via Flit retransmission. This layered approach achieves high reliability with low overhead.

8. FEC and Width Changes

L0p Width Change

9. Implementation Considerations

Hardware Requirements

Power Considerations