L0p Power State Complete Guide

1. What is L0p?

What is L0p?

L0p is a new power state introduced in PCIe 6.0 that enables dynamic link width reduction while maintaining the link in an operational state. Unlike L0s or L1 which stop data transmission, L0p reduces the number of active lanes while continuing to transmit data on the remaining lanes.

Key Characteristics

Flit Mode Only: L0p requires Flit Mode operation
Width Reduction: Dynamically reduce link width (e.g., x16→x8→x4)
Continuous Operation: Traffic continues on active lanes
Low Latency: Fast width change without full recovery
Power Proportional: Power scales with bandwidth usage

L0p vs Other Power States

State	Traffic	Width	Exit Latency	Power Saving
L0	Full	Full	N/A	None
L0p	Reduced	Reduced	< 1 μs	Proportional
L0s	None	Full (idle)	< 1 μs	Moderate
L1	None	N/A	2-32 μs	High

2. Why L0p?

Why is L0p needed?

Traditional power management (L0s/L1) cannot save power when there is continuous low-bandwidth traffic. L0p enables power savings proportional to actual bandwidth usage by reducing active lanes while maintaining data flow.

Use Case Examples

NVMe SSD: Idle reads at x1 width instead of x4
Network Card: Low traffic uses fewer lanes
GPU: Desktop workload vs gaming workload
Storage Controller: Background activity on reduced width

Power Savings Model

    Power
       ▲
       │
  Full │████████████████████████████████   L0 (Full Width)
       │
  3/4  │████████████████████████           x12 from x16
       │
  1/2  │████████████████                   L0p (Half Width)
       │
  1/4  │████████                           L0p (Quarter Width)
       │
       └──────────────────────────────────► Traffic Load
       
    L0p enables power proportional to bandwidth need

3. L0p Width Options

Supported Width Reductions

Trained Width	L0p Width Options
x16	x8, x4, x2, x1
x8	x4, x2, x1
x4	x2, x1
x2	x1
x1	(L0p not applicable)

Lane Selection

Active lanes are always the lower-numbered lanes
Example: x16→x4 uses Lanes 0-3, idles Lanes 4-15
Symmetric width required on both ports

4. L0p Entry/Exit Protocol

Entry Procedure

    Port A                                    Port B
       │                                         │
       │ 1. Decision to reduce width             │
       │                                         │
       │──── L0p Width Request DLLP ────────────►│
       │     (Target Width = x4)                 │
       │                                         │
       │◄─── L0p Width Ack DLLP ─────────────────│
       │     (Accepted)                          │
       │                                         │
       │ 2. Both ports prepare for width change  │
       │                                         │
       │──── Flit with L0p Entry ───────────────►│
       │     (on all active lanes)               │
       │                                         │
       │ 3. Transition to reduced width          │
       │    Lanes 4-15 enter electrical idle     │
       │                                         │
       │◄═══ Data on x4 (Lanes 0-3) ═══════════►│
       │                                         │

Exit Procedure

    Port A                                    Port B
       │                                         │
       │ 1. Decision to increase width           │
       │    (traffic demand increased)           │
       │                                         │
       │──── L0p Width Request DLLP ────────────►│
       │     (Target Width = x16)                │
       │                                         │
       │◄─── L0p Width Ack DLLP ─────────────────│
       │                                         │
       │ 2. Wake idle lanes (4-15)               │
       │    Short retraining if needed           │
       │                                         │
       │ 3. Resume full width operation          │
       │                                         │
       │◄═══ Data on x16 (Lanes 0-15) ═════════►│
       │                                         │

Entry/Exit Latency

Entry Latency: < 1 μs (width reduction)
Exit Latency: < 1 μs (width increase)
No Recovery Required: Much faster than L0s/L1 exit

5. L0p DLLPs

L0p Width Request DLLP

Sent by either port to request width change
Contains Target Link Width field
Requires acknowledgment before change

L0p Width Ack DLLP

Acknowledges width change request
Can accept or reject proposal
Both ports must agree on new width

Target Link Width Field

Value	Target Width
0001b	x1
0010b	x2
0100b	x4
1000b	x8
1111b	Full (trained) width

6. L0p Capability and Control

L0p Capability Fields

L0p Supported: Port supports L0p
L0p Supported Widths: Which reduced widths supported
L0p Entry Latency: Time to enter L0p
L0p Exit Latency: Time to exit L0p

L0p Control Fields

L0p Enable: Enable/disable L0p
L0p Request: Software request for width change
Target Link Width: Requested L0p width

L0p Status Fields

Current L0p State: In L0p or not
Current Link Width: Active width

7. Flit Mode Integration

Why Flit Mode Required?

256-byte Flit structure enables clean width transitions
FEC provides error protection during width changes
DLP can signal width change boundaries
Simplified protocol vs byte-level width changes

Width Change Signaling in Flit

DLP contains width change control bits
Width change aligned to Flit boundaries
FEC reconfigured for new width

8. System Considerations

When to Use L0p

Continuous low-bandwidth traffic
Predictable traffic patterns
Power-sensitive applications
When L0s/L1 cannot be used (traffic present)

When Not to Use L0p

Bursty high-bandwidth traffic (latency penalty)
Latency-critical applications
x1 links (no width reduction possible)

Driver Considerations

Monitor bandwidth utilization
Trigger width changes based on traffic patterns
Balance power savings vs latency impact

Important: L0p and Performance

L0p reduces available bandwidth. Software must carefully manage width changes to avoid performance impact during bandwidth-intensive operations. Hysteresis and traffic prediction can help optimize L0p usage.